1. Field of the Invention
The present invention relates to an IC card and, more particularly, to a command input IC card having a plurality of built-in memory semiconductor elements for electrically storing and batch-erasing data.
2. Description of the Related Art
FIG. 2 is a block diagram showing the structure of the circuitry on a conventional command type IC card. Two memory semiconductor elements 2 and 3 having similar structures are connected to an address decoder 1. Each of the memory semiconductor elements 2 and 3 is a command input element that receives commands from outside the card for determining operating modes on the basis of the commands, and is capable of electrically writing and batch-erasing data. A card enable signal line 6 and a signal line 7a, one of the signal lines running through an address bus 7, are connected to the address decoder 1. The address bus 7, a read enable signal line 8, a write enable signal line 9, a data bus 10 and a program power supply line 11 are all connected to both of the memory semiconductor elements 2 and 3. The memory semiconductor element 2 is connected to the address decoder 1 by a chip enable signal line 12; similarly, the memory semiconductor element 3 is connected to the address decoder 1 by another chip enable signal line 13. The card enable signal line 6, the read enable signal line 8 and the write enable signal line 9 are pulled-up to power source voltages by resistors 16, 17 and 18, respectively.
FIG. 3 shows the inner structure of the memory semiconductor element 2. The address bus 7 is connected to a memory cell array 20 through an X address decoder 21 and a Y address decoder 22. The data bus 10 is connected to the memory cell array 20 through a data input/output circuit 24 (a data I/O circuit 24). A command latch circuit 25 is connected to the data bus 10. A control logic circuit 23 is connected to the X address decoder 21, the Y address decoder 22, the data I/O circuit 24 and the command latch circuit 25. The chip enable signal line 12, the read enable signal line 8, the write enable signal line 9 and the program power supply line 11 are all connected to the control logic circuit 23.
When data is read from the memory semiconductor element 2, the level of the chip enable signal line 12 and that of the read enable signal line 8 are both low, whereas the level of the write enable signal line 9 is high. At the same time, an ordinary supply voltage is applied to the program power supply line 11. When a desired address is specified on the address bus 7, the X and Y address decoders 21 and 22 select a memory cell corresponding to the specified address from the memory cell array 20. Data stored in this memory cell is output to the data bus 10 via the data I/O circuit 24.
When data is written, i.e., stored, or batch-erased, a program voltage is applied to the program power supply line 11, and the level of the read enable signal line 8 is made high, whereas the level of the chip enable signal line 12 and that of the write enable signal line 9 are both made low. Under these conditions, when a command is input through the data bus 10, it is retained by the command latch circuit 25. Whether data is written or batch-erased depends on the command in the command latch circuit 25.
When data is written, the level of the chip enable signal line 12 and that of the write enable signal line 9 are both low, and the level of the read enable signal line 8 is high. The data is input to the data bus 10 and is thereby written into a desired address. The level of the chip enable signal line 12 and that of the read enable signal line 8 are both low, whereas the level of the write enable signal line 9 is high. The written data is read on the data bus 10 and is verified by a predetermined algorithm.
When data is batch-erased, in the same manner as in writing, the level of the chip enable signal line 12 and that of the write enable signal line 9 are both made low, whereas the level of the read enable signal line 8 is made high. After the contents of all the memory cells in the memory array 20 have been erased, the level of the chip enable signal line 12 and that of the read enable signal line 8 are both made low, whereas the level of the write enable signal line 9 is made high. An algorithm different from that used in writing verifies batch erasure.
When the level of the chip enable signal line 12 is high, the memory semiconductor element 2 becomes inactive and does not perform any operation, regardless of the levels of the other signal lines.
In this way, to actuate the IC card, shown in FIG. 2, having the built-in memory semiconductor elements 2 and 3, a predetermined voltage is applied to the program power supply line 11, and the level of the card enable signal line 6 is made low. A card enable signal is decoded on the basis of a part of an address signal which is input to the address decoder 1 through the signal line 7a. As a result, an a low level chip enable signal is output from the address decoder 1 to one of the memory semiconductor elements 2 and 3 in accordance with an address specified by the address signal. The memory semiconductor element having received the chip enable signal becomes active, thus making it possible to perform the various operations mentioned above.
The address decoder 1 makes the level of one chip enable signal line 12, connected to the memory semiconductor element 2, high, and also makes the level of the other chip enable signal line 13, connected to the memory semiconductor element 3, low, or vice versa. Therefore, when the contents stored in all the memory semiconductor elements 2 and 3 in the entire IC card are erased, the contents are erased element by element. Thus the contents stored in the IC card cannot be batch-erased. For this reason, it takes an enormous amount of time to erase the contents stored in the entire IC card.